1. Field of the Invention
The present invention relates to memory access, and in particular to an improved multiaccess circuit for a memory, capable of performing a smooth processing when a multiaccess situation occurs in the memory in a process of a pipeline.
2. Description of the Conventional Art
FIGS. 1A to 1D are diagrams illustrating a four-steps pipeline.
A pipeline of a processor is a bus operation process during execution of instructions, and in case of the four-steps pipeline, the process is performed in the order of instruction fetch.fwdarw.decode.fwdarw.operand fetch.fwdarw.execution.
That is, as shown in FIGS. 1A to 1D, when an instruction 1 (INT1) is decoded after being fetched, an instruction 2 (INT2) is fetched. When the instruction 1 (INT1) is operand-fetched, the instruction 2 (INT2) is decoded and an instruction 3 (INT3) is fetched. When the instruction 1 (INT1) is executed, the instruction 2 (INT2) is operand-fetched, the instruction 3 (INT3) is decoded, and an instruction 4 (INT4) is newly fetched. As described above, each instruction is independently performed.
FIG. 2 illustrates a conventional processor for operating the 4-steps pipeline for the instructions.
As shown therein, the processor includes an instruction decoder 10 for decoding a program outputted from a ROM 13 and outputting a control signal for a pipeline operation; an addressing unit 11 for outputting an address signal of the ROM 13 and RAM 14 in accordance with the control of the instruction decoder 10; a memory access unit 12 for outputting a ROM_ADD signal for accessing the ROM 13 and a ROM_ADD signal for accessing the RAM 14; and an arithmetic operator 15 for operating a data outputted from the RAM 14 by the program outputted from the ROM 13 in accordance with the control of the instruction decoder 10.
The operation of the thusly constructed conventional processor will be described with reference to the accompanying drawings.
First, the addressing unit 11 generates the ROM address ROM_ADD, as shown in FIG. 3B, by each cycle of a clock signal CLK, and the ROM 13 loads a corresponding program as shown in FIG. 3C into a program bus PBUS in accordance with the ROM address ROM_ADD. The memory access unit 12 receives the address ADDR outputted from the addressing unit 11, accesses data of the RAM 14 by the RAM address RAM_ADD, and outputs the address to the arithmetic operator 15 over a data bus DBUS. Accordingly, the arithmetic operator 15 operates the data outputted from the RAM 14 in accordance with the control of the instruction decoder 10. That is, for a first cycle t1 of the clock signal CLK, the instruction decoder 10 receives a program outputted from the ROM 13, fetches an instruction 1, and synchronizes the instruction 1 which is fetched with the clock signal CLK as shown in FIGS. 3C and 3D. Next, for a second cycle t2 of the clock signal CLK, the instruction decoder 10 simultaneously decodes the fetched instruction 1 and fetches an instruction 2 as shown in FIGS. 3D and 3E.
For a third cycle t3 of the clock signal CLK, the instruction decoder 10 outputs a control signal by interpreting the decoded instruction 1, decodes the fetched instruction 2, and simultaneously fetches an instruction 3.
For a fourth cycle t4 of the clock signal CLK, the instruction decoder 10 generates a control signal with respect to the instruction 2, decodes the fetched instruction 3, and fetches an instruction 4, and the arithmetic operator 15 operates the data outputted from the RAM 14 in accordance with the control signal with respect to the instruction 1.
Thereafter, each process is independently and repeatedly carried out without any collision.
However, it is also possible to only employ the RAM, which can be applied as program and data, without separately using the ROM and RAM as shown in FIG. 2, or using the RAM 14 as the program and data by downloading a new program from an external memory to the RAM 14 when the ROM 13 and RAM 14 are separately provided.
However, in case where the multiaccess to the RAM 14 employed as the data and program occurs, that is when the program and data stored in the RAM 14 are simultaneously requested, the conventional processor has no circuit for arbitrating the multiaccess, thus the collision among the instructions may occur and such collision may lead to an erroneous operation of the processor.